This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to the manufacture and testing of embedded static random access memories (SRAMs) in large-scale integrated circuits.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, in an attempt to write a low logic level to storage node SNT of cell 2 of FIG. 1, if bit line BLTk is unable to sufficiently discharge storage node SNT to a sufficient level to trip the inverters, cell 2 may not latch to the desired data state.
Cell stability failures are the converse of write failures—while a write failure occurs if a cell is too stubborn in changing its state, a cell stability failure occurs if a cell changes its state too easily. Noise of sufficient magnitude coupling to the bit lines of unselected cells, for example during a write to a selected memory cell in the same row, can cause a false write of data to unselected cells in that same row. In effect, such write cycle noise can be of sufficient magnitude as to trip the inverters of one or more of the unselected cells (i.e., the “half-selected” cells in unselected columns of the selected row). The possibility of such stability failure is exacerbated by device mismatch and variability, as discussed above.
As known in the art, an important measure of the functionality of an SRAM memory cell is the minimum power supply voltage (i.e., the differential voltage between array power supply voltage Vdda and array reference voltage Vssa in the arrangement of FIG. 1) at which that memory cell can be successfully written and read. It is desirable that this minimum power supply voltage be as low as possible, particularly for memories to be implemented in portable and other battery-powered or otherwise power-sensitive applications. This minimum power supply voltage is referred to in the art as “Vmin”.
In modern SRAMs constructed with sub-micron feature sizes, the measure of Vmin will vary from cell to cell within an array, and therefore within the same multiple-array or multiple-block integrated circuit. This cell-to-cell variation stems from such known effects as random dopant fluctuation (“RDP”), line-end roughness (“LER”), and the like, which introduce observable variations among populations of transistors in the deep sub-micron regime. As a result, the Vmin for a particular memory will be determined by the cell within that memory with the poorest (i.e., highest) Vmin measurement.
Furthermore, it has been observed that Vmin tends to degrade over operating life in conventional CMOS SRAMs. Important mechanisms in this regard include negative bias temperature instability (“NBTI”), which appears as an increase in threshold voltage of p-channel MOS transistors over operating time, and “Random Telegraph Noise” (“RTN”) caused by physical defects within MOS gate dielectric that can trap charge during device operation, and thus modulate the threshold voltage of the transistor. These and other mechanisms can cause variations in transistor threshold voltage of as much as 10 to 20 mV, which noticeably affects transistor performance, and adversely affects memory cell Vmin.
Conventional manufacturing test flows for sub-micron CMOS SRAMs now commonly includes a “guardband” voltage to the power supply voltage during one or more functional tests. One or more functional screening tests are performed at this reduced power supply voltage to screen out (or invoke replacement via redundant rows or columns) those devices with a Vmin that is close to the pass/fail threshold at manufacture, within a guardband margin corresponding to the expected NBTI drift over the desired operating life, and perhaps also accounting for expected RTN effects and for other factors.
It is, of course, important to precisely set the power supply voltage at which an SRAM array is functionally tested, especially when testing the SRAM using these guardband voltages for screening out bits or arrays vulnerable to mechanisms such as NBTI or RTN effects. Assuming accurately designed screen conditions, if the test power supply voltage at the SRAM array is actually higher than desired, the SRAM will be “undertested”, in that truly vulnerable or failing memory cells will pass the screening test and thus escape into the field; the test yield will be over-estimated as a result. Conversely, if the test power supply voltage at the SRAM array is actually lower than desired, the SRAM will be “overtested” in that some memory cells will be deemed to fail the screen that would not fail the true test, which will reduce the test yield without a noticeable improvement the reliability or functionality of the device in its eventual system usage.
By way of further background, some large-scale integrated circuits, such as the so-called “system-on-a-chip” (“SoC”) integrated circuits, include a pad or pin at which a power supply voltage may be applied during test of various functions on that integrated circuit, such functions including memory arrays in such integrated circuits. This pad or pin is connected in parallel to those functions to be tested, such that all receive the same power supply voltage. It is known in the art to apply a fixed adjustment to the power supply voltage applied to such a pad or pin during test, to compensate for resistive voltage drop in the conductors between the pad or pin and the various functions or arrays.